A nanopower, high PSRR full CMOS voltage reference circuit consisting of subthreshold MOSFETs

A sub-1-V nanopower full CMOS voltage reference circuit was proposed in TSMC 0.18μm CMOS process in this paper. The circuit consists of a self-regulating technique circuit, a proportional to absolute temperature (PTAT) current circuit and active load circuit. In order to reduce power consumption and save area of the chip, the proposed circuit contains only MOSFETs, avoiding the use of resistors. Cadence Spectre simulation results show that the temperature coefficient of the output voltage was 66.9 ppm/°C in a range from -40 to 120°C, and the line sensitivity was 197.5 ppm/V in a supply voltage range of 1-3 V Meanwhile, the power supply rejection ratio (PSRR) of the voltage reference achieved -93.22 dB@DC and -15.45 dB@10MHz, and the proposed circuit merely consumed 0.23 μW of power at room temperature. Our proposed circuit would be suitable for use in subthreshold-operated and power-sensitive large scale integrated circuit.