Title :
Architecture and performance of 3-dimensional SOI circuits
Author :
Rongtian Zhang;K. Roy;D.B. Janes
Author_Institution :
Purdue Univ., West Lafayette, IN, USA
fDate :
6/21/1905 12:00:00 AM
Abstract :
In this paper, potential three-dimensional SOI CMOS VLSI circuit structures are laid out. Chip area, layout complexities, process costs, and impact on circuit performance are compared and discussed.
Keywords :
"Silicon on insulator technology","Integrated circuit interconnections","Costs","Circuit optimization","Wire","Circuit synthesis","Buildings","CMOS technology","Semiconductor device measurement","Size measurement"
Conference_Titel :
SOI Conference, 1999. Proceedings. 1999 IEEE International
Print_ISBN :
0-7803-5456-7
DOI :
10.1109/SOI.1999.819850
