Title :
Novel fault-tolerant techniques for high capacity RAMs
Author :
Hsu, Chih-Hsien ; Lu, Shyue-Kung ; Kuo, Sy-Yen
Author_Institution :
Dept. of Electron. Eng, Fu Jen Catholic Univ., Taipei, Taiwan
Abstract :
In the area of high capacity RAMs, the memory columns (rows), including the redundancies, are partitioned into column blocks (row blocks), respectively. If the replacement is performed at the row-block level, then a row block-based FTM (RBFTM) system is used. Alternatively, if the replacement is performed at the column-block level, then a column block-based FTM (CBFTM) system is used. If both approaches are incorporated into a memory chip, then the hybrid FTM (HFTM) system is achieved. Experimental results and analysis show that our fault-tolerant architectures can improve the yield for memory fabrication significantly. The reconfiguration mechanism requires almost negligible hardware overhead for high capacity memories. Moreover, the repair rates among different fault-tolerant strategies are also compared
Keywords :
fault tolerant computing; memory architecture; microprocessor chips; random-access storage; reconfigurable architectures; redundancy; CBFTM; HFTM; RBFTM; built-in self-repair; column block-based FTM; column-block level; divided bit-line; divided word-line; fault tolerance; fault-tolerant architectures; fault-tolerant strategies; fault-tolerant techniques; high capacity RAMs; high capacity memories; hybrid FTM; memory chip; memory columns; memory fabrication; negligible hardware overhead; reconfiguration mechanism; redundancies; repair rates; row block-based FTM; Circuit faults; Fault detection; Fault tolerance; Hardware; Laser beam cutting; Manufacturing; Random access memory; Read-write memory; Redundancy; System-on-a-chip;
Conference_Titel :
Dependable Computing, 2001. Proceedings. 2001 Pacific Rim International Symposium on
Conference_Location :
Seoul
Print_ISBN :
0-7695-1414-6
DOI :
10.1109/PRDC.2001.992673