Framework for synthesis of virtual pipelines

Virtual pipelining allows designs of arbitrary size to execute on finite sized FPGA devices. It allows pipelined designs to be efficiently configured on an FPGA by overlapping the reconfiguration time of a pipeline stage with the execution time of previous pipeline stages. This technique produces performance improvement up to an order of 5 versus a nonpipelined execution of a design. We extend this principle for handling large designs that were previously too large to fit on an FPGA. This paper presents a framework for automatically synthesizing virtual pipelines on a Virtex FPGA. We also suggest criteria for extending our approach to nonVirtex FPGAs