An analog decoder for concatenated magnetic recording schemes

Author

Amat, A. Graell I ; Montorsi, G. ; Neviani, A. ; Xotta, A.

Author_Institution

Politecnico di Torino, Italy

Volume

3

fYear

2002

fDate

2002

Firstpage

1563

Abstract

This paper presents an all-analog iterative decoding network for an EPR4 magnetic recording system. A powerful serially concatenated architecture is considered, consisting of a simple outer code, an interleaver with reasonable size and a rate 1 EPR4 channel as inner code. The analog chip design is based on analog 0.18 μm CMOS technology. Simulation results for both digital and analog implementations are shown. Practical implementation issues such as considerations of mismatch effects over performance are also discussed.

Keywords

CMOS analogue integrated circuits; concatenated codes; interleaved codes; iterative decoding; magnetic recording; turbo codes; 0.181 micron; EPR4 magnetic recording system; all-analog iterative decoding network; analog CMOS technology; analog chip design; analog decoder; code rate; concatenated magnetic recording; digital CMOS technology; inner code; interleaver size; mismatch effects; mixed structural-behavioral simulation; outer code; serially concatenated architecture; simulation results; transistor-level simulation; turbo codes; CMOS technology; Chip scale packaging; Computational modeling; Concatenated codes; Convolutional codes; Energy consumption; Iterative algorithms; Iterative decoding; Magnetic recording; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, 2002. ICC 2002. IEEE International Conference on

Print_ISBN

0-7803-7400-2

Type

conf

DOI

10.1109/ICC.2002.997112

Filename

997112