DocumentCode :
3795907
Title :
Theoretical and experimental evaluation of high-voltage CMOS inverters
Author :
N.D. Jankovic;E. Bushehri
Author_Institution :
Fac. of Electron. Eng., Nis Univ., Serbia
Volume :
141
Issue :
3
fYear :
1994
fDate :
6/1/1994 12:00:00 AM
Firstpage :
162
Lastpage :
166
Abstract :
A high-voltage CMOS technology featuring a 45 V maximum blocking voltage is described. The transistor output characteristics at high voltages are simulated by employing an impact-ionisation current model and the results are verified by measurements on fabricated test structures. Proper inverter operation is maintained up to a supply voltage of 35 V, despite a large impact-ionisation-induced mismatch in the pMOS and nMOS output characteristics at high voltages. In addition, simulation results reveal that impact-ionisation currents have little effect on inverter performance in terms of power dissipation. The inverter delay times are also found to be independent of the transistor sizes for supply voltages of above 25 V; therefore, small-geometry transistors can be used to reduce the overall area of the high-voltage circuits.
Keywords :
"CMOS integrated circuits","Impact ionization","Inverters","Power integrated circuits"
Journal_Title :
IEE Proceedings - Circuits, Devices and Systems
Publisher :
iet
ISSN :
1350-2409
Type :
jour
DOI :
10.1049/ip-cds:19949901
Filename :
296535
Link To Document :
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