An enhanced Q-sequence augmented with empty-room-insertion and parenthesis trees

Author

Zhuang, Changwen ; Sakanushi, Keishi ; Jin, Liyan ; Kajitani, Yoji

Author_Institution

Inf. & Media Sci., Univ. of Kitakyusyu, Fukuoka, Japan

fYear

2002

fDate

2002

Firstpage

61

Lastpage

68

Abstract

After the discussion on the difference between floorplanning and packing in VLSI placement design, this paper adapts the floorplanner that is based on the Q-sequence to a packing algorithm. For the purpose, some empty room insertion is required to guarantee not to miss the optimum packing. To increase the performance in packing, a new move that perturbs the floorplan is introduced in terms of the parenthesis-tree pair. A simulated annealing based packing search algorithm was implemented. Experimental results showed the effect of empty room insertion

Keywords

C++ language; VLSI; circuit layout CAD; circuit optimisation; integrated circuit layout; simulated annealing; trees (mathematics); VLSI placement design; empty-room-insertion; enhanced Q-sequence; optimum packing; packing algorithm; parenthesis trees; simulated annealing; Algorithm design and analysis; Circuit simulation; Circuit synthesis; Compaction; Design methodology; History; Optimal control; Paper technology; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Conference_Location

Paris

ISSN

1530-1591

Print_ISBN

0-7695-1471-5

Type

conf

DOI

10.1109/DATE.2002.998250

Filename

998250