Macromodeling of digital I/O ports for system EMC assessment

Author

Stievano, I.S. ; Chen, Z. ; Becker, D. ; Canavero, F.G. ; Katopis, G. ; Maio, I.A.

Author_Institution

Dipt. di Elettronica, Politecnico di Torino, Italy

fYear

2002

fDate

2002

Firstpage

1044

Lastpage

1048

Abstract

This paper addresses the development of accurate and efficient behavioral models of digital integrated circuit input and output ports for EMC and signal integrity simulations. A practical modeling process is proposed and applied to some example devices. The modeling process is simple and efficient, and it yields models performing at a very high accuracy level

Keywords

digital integrated circuits; electromagnetic compatibility; integrated circuit modelling; integrated circuit reliability; EMC simulations; behavioral models; digital I/O ports; digital integrated circuit input ports; digital integrated circuit output ports; macromodeling; model accuracy; modeling process; signal integrity simulations; system EMC assessment; Circuit simulation; Digital integrated circuits; Driver circuits; Electromagnetic compatibility; Electronic switching systems; Equations; Integrated circuit modeling; Parametric statistics; State estimation; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Conference_Location

Paris

ISSN

1530-1591

Print_ISBN

0-7695-1471-5

Type

conf

DOI

10.1109/DATE.2002.998429

Filename

998429

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=379764