Title :
Effect of underfill fillet configuration on flip chip package reliability
Author :
Nguyen, L. ; Nguyen, H.
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
Abstract :
With flip chip processing, sufficient underfill material needs to be present during assembly to ensure a fillet around the die. The volume of underfill used governs the fillet shape, regardless of the application method, e.g., standard capillary deposition, no-flow, or wafer level underfill. There has been more interest with the latter method due to the paradigm shift in processing. Advantages and challenges exist with wafer level underfill. One concern is the fillet shape obtainable for a given pre-applied film thickness and flow characteristics, which are governed by the curing mechanisms. This paper presents experimental and modeling results of the effects of fillet configurations on flip chip reliability. Configurations with and without fillets were made with different underfills on flip chip dies on ceramic substrates. The packages were thermally cycled, electrically tested and scanned with acoustic microscopy to check for interfacial delamination. Finite element models were also generated for the different configurations and materials to provide relative merits on the material/configuration aspects. The results indicated that the presence of fillets is as equally important as the selection of the underfill material for the best thermal cycling performance. Thus, ensuring that the proper coating thickness is obtained will be critical to good die filleting and package reliability in wafer level underfill processing.
Keywords :
acoustic microscopy; delamination; encapsulation; flip-chip devices; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; life testing; acoustic microscopy; application method; ceramic substrates; curing mechanisms; fillet shape; film thickness; flip chip dies; flip chip package reliability; flow characteristics; interfacial delamination; no-flow; package reliability; standard capillary deposition; thermal cycling performance; underfill fillet configuration; wafer level underfill; Acoustic testing; Assembly; Ceramics; Curing; Flip chip; Packaging; Semiconductor device modeling; Shape; Substrates; Wafer scale integration;
Conference_Titel :
Electronics Manufacturing Technology Symposium, 2002. IEMT 2002. 27th Annual IEEE/SEMI International
Print_ISBN :
0-7803-7301-4
DOI :
10.1109/IEMT.2002.1032769