Design and analysis of a 0.6 V-operating merged CMOS-bipolar SRAM cell

A novel CMOS-bipolar SRAM cell has been analysed for a supply voltage of 0.6 V. It incorporates cross-coupled CMOS and complementary bipolar inverters with two NMOS access transistors. Standard double-end write operation with single-end read operation from the bipolar node is discussed. A column circuitry to accompany the cell is also proposed. Simulation results using a standard 1.5 /spl mu/m CMOS technology show an access time of 5-7 ns with very low standby and active power dissipation of 18 nW/bit and 2.2 /spl mu/W/bit, respectively. The cell area is found to be less than that of the corresponding full-CMOS SRAM cell.