A Novel 3D Integration Scheme for Backside Illuminated CMOS Image Sensor Devices

Author

Cheng-Ta Ko ; Zhi-Cheng Hsiao ; Hsiang-Hung Chang ; Dian-Rong Lyu ; Chao-Kai Hsu ; Huan-Chun Fu ; Chun-Hsien Chien ; Wei-Chung Lo ; Kuan-Neng Chen

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

14

Issue

2

fYear

2014

fDate

Jun-14

Firstpage

715

Lastpage

720

Abstract

A novel backside-illuminated CMOS image sensor (BSI-CIS) scheme and process are developed and demonstrated. This innovative scheme can be realized without fusion oxide bonding and through-silicon via (TSV) fabrication. This wafer-level TSV-less BSI-CIS scheme includes transparent ultrathin silicon (~ 3.6 μm) and uses several bonding technologies. The characterization and assessment results indicate that the integration scheme possesses excellent electrical integrity and reliability. In addition, good quality results of the image functional test demonstrate the excellent performance of this scheme. This novel scheme also provides a realizable low-cost solution for the next-generation CIS and further 3-D novel BSI-CIS scheme.

Keywords

CMOS image sensors; elemental semiconductors; integrated circuit reliability; silicon; wafer bonding; 3D integration scheme; Si; backside-illuminated CMOS image sensor; bonding technologies; electrical integrity; reliability; transparent ultrathin silicon; wafer-level TSV-less BSI-CIS scheme; Bonding; CMOS image sensors; Educational institutions; Reliability; Silicon; Three-dimensional displays; Through-silicon vias; 3D integration; CMOS image sensor; backside illuminated;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2014.2311887

Filename

6774458