• DocumentCode
    3833388
  • Title

    Note on digital-summation threshold-logic gates

  • Author

    V.C.V. Pratapa Reddy;P.S. Neelakantaswamy

  • Author_Institution
    Indian Institute of Technology, Department of Electrical Engineering, Madras, India
  • Volume
    121
  • Issue
    10
  • fYear
    1974
  • fDate
    10/1/1974 12:00:00 AM
  • Firstpage
    1085
  • Lastpage
    1086
  • Journal_Title
    Proceedings of the Institution of Electrical Engineers
  • Publisher
    iet
  • ISSN
    0020-3270
  • Type

    jour

  • DOI
    10.1049/piee.1974.0253
  • Filename
    5251722
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3833388