Analysis of clock jitter effects in wideband sigma-delta modulators for rf-applications

This paper presents a theoretical overview and analysis of the main types of clock jitter in a switched capacitor (SC) Sigma-Delta (ΣΔ) Analog-to-Digital-Converter (ADC). We start by defining the different types of jitter and proceed to analyze their impact both theoretically and by simulations. The main jitter assumption throughout this paper is that it is stochastic in nature. Using this assumption each jitter type´s effect on the ΣΔ output is calculated and simulated. One type of jitter is often neglected in textbooks and other papers due to assumptions which need to be clarified. We conclude that it is important to consider this type of jitter because it has a strong impact. Furthermore, it is important to characterize each jitter type not only with severity but also how difficult it is to suppress or the likelihood of jitter presence which, of course, is dependent on architecture and application.