A B-s complement continuous valued digit adder

This paper presents the first VLSI implementation of test circuitry for the continuous valued digits number system (CVNS). The CVNS is a recently introduced number system that uses a set of analog digits; the lower-order digits being used only to correct inaccuracies in the higher order digits. In order to provide a vehicle for the test implementation, an 8 bit, radix 2, B-s complement CVNS adder is designed using current mode analog circuitry. This initial test circuit is purposely designed with very conservative performance parameters, solely with the aim of demonstrating the viability of the representation and associated arithmetic circuitry. The test structures includes an 8 bit D/A, a modulo operation circuit, and an analog correction circuit. These blocks are combined with two new circuits to realize a novel design approach to CVNS addition that guarantees more than sufficient precision in the generation of the least significant continuous valued digit (CVD), and high tolerance to implementation error.