SoC design using behavioral level virtual components

While SoC design and virtual component (VC) reuse are on their way to becoming unavoidable practices, the increasing complexity of applications and of VCs themselves will soon require new design methodologies. Designing faster and providing highly flexible components will require raising the abstraction level and benefiting from higher-level integration tools. High level synthesis (HLS) is a promising approach to quickly generate RTL architectures from a behavioral description. While flexibility of currently used soft IPs (intellectual properties) is mainly limited to optimizing the logic synthesis flow - even using genericity -, behavioral IPs introduce architectural flexibility and thus allow a closer adaptation to the requirements of a target application. In this paper, a design approach for efficient VC design and reuse at the behavioral level is presented.