A low power fault secure timer implementation based on the Gray encoding scheme

In this paper a novel architecture for low power fault-secure synchronous timer that relies on the Gray-coding scheme, is introduced. This timer is based on the Parity prediction technique and it can detect any single stuck-at-fault, transient or permanent, in real-time. A thorough analysis of the timer´s architecture and its behavior at the occurrence of any single fault on the circuit is presented, to ensure the fault-secure property of the timer. Also the hardware and power requirements of this fault-secure timer are examined, in comparison to other dominating safe operation timers based on existing fault-secure counters, to show the benefits that can be derived from the use of this timer scheme.