Efficiency of dual supply voltage logic synthesis for low power in consideration of varying delay constraint strictness

In this paper, we investigate the efficiency of logic-level power optimization through dual supply voltage scaling (DSVS). In our experiments, we employed a novel power-driven logic synthesis methodology which enables DSVS in addition to state-of-the-art optimization techniques. Using that methodology, we optimized benchmark circuits subject to varying delay constraints and compared the results to those obtained from power-driven single supply voltage (SSV) logic synthesis and from global supply voltage scaling (GSVS). In the case of relaxed delay constraints, we observed that DSVS generally further reduced the power consumption of combinational circuits by up to 16%, while GSVS actually led to higher power consumption in 50% of the test cases, compared with SSV optimization. Furthermore, GSVS always resulted in significantly larger area. In the case of strictest delay constraints, where GSVS is not applicable, DSVS further reduced the power consumption of sequential circuits by up to 17% compared with the results of SSV power optimization.