On sparse matrix-vector multiplication with FPGA-based system

In this paper we report on our experimentation with the use of FPGA-based system to solve the irregular computation problem of evaluating y = Ax when the matrix A is sparse. The main features of our matrix-vector multiplication algorithm are (i) an organization of the operations to suit the FPGA-based system ability in processing a stream of data, and (ii) the use of distributed arithmetic technique together with an efficient scheduling heuristic to exploit the inherent parallelism in the matrix-vector multiplication problem. The performance of our algorithm has been evaluated with an implementation on the Pamette FPGA-based system.