• DocumentCode
    385658
  • Title

    Modeling switching activity using cascaded Bayesian networks for correlated input streams

  • Author

    Bhanja, Sanjukta ; Ranganathan, N.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    388
  • Lastpage
    390
  • Abstract
    We represent switching activity in VLSI circuits using a graphical probabilistic model based on cascaded Bayesian networks (CBNs). We develop an elegant method for maintaining probabilistic consistency in the interfacing boundaries across the CBNs during the inference process using a tree-dependent (TD) probability distribution function. A tree-dependent (TD) distribution is an approximation of the true joint probability function over the switching variables, with the constraint that the underlying Bayesian network representation is a tree. The tree approximation of the true joint probability function can be arrived at using a maximum weight spanning tree (MWST) built using pairwise mutual information between switchings at two signal lines. Further we also develop a TD distribution based method to model correlations among the primary inputs which is critical for accuracy in Bayesian modeling of switching activity. Experimental results for ISCAS circuits are presented to illustrate the efficacy of the proposed methods.
  • Keywords
    VLSI; belief networks; combinational circuits; integrated circuit modelling; probability; trees (mathematics); Bayesian modeling; ISCAS circuits; VLSI circuits; cascaded Bayesian networks; combinational circuits; correlated input streams; graphical probabilistic model; inference process; interfacing boundaries; maximum weight spanning tree; pairwise mutual information; primary inputs; probabilistic consistency; signal lines; switching activity modeling; switching variables; tree approximation; tree-dependent probability distribution function; true joint probability function; Bayesian methods; Combinational circuits; Computational efficiency; Computer networks; Coupling circuits; Delay estimation; Fuses; Switching circuits; Tree graphs; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on
  • ISSN
    1063-6404
  • Print_ISBN
    0-7695-1700-5
  • Type

    conf

  • DOI
    10.1109/ICCD.2002.1106799
  • Filename
    1106799