Incorporating area-time flexibility to a binary signed-digit adder

Computer arithmetic operations based on redundant signed-digit representation systems such as the BSD (binary signed-digit) number system execute faster due to limited carry propagation additions. In this paper, area-time measures for fully parallel, serial and pipelined implementations of a well-known BSD addition technique are presented. All three versions were synthesized at gate level using 0.35 μm CMOS cell-based libraries. Our results show that while the fully parallel method provides the fastest with highest area complexity, both the serial and pipelined approaches facilitate scalable implementations that lend well for area-time optimal solutions in VLSI.