Interface generation for concurrent processes during hardware/software co-synthesis

Author

De Araujo, Cristiano C. ; Barros, Edna

Author_Institution

Centro de Inf., Univ. Fed. de Pernambuco, Recife, Brazil

fYear

2002

fDate

2002

Firstpage

109

Lastpage

114

Abstract

This paper describes an interface model, which is being used in the PISH co-design system. This model is based on layers, and tries to keep the interface generation as independent as possible of the underlying target architecture. The proposed interface structuring, in three layers, provides abstraction of the communication implementation at process level and makes the interface generation process easier.

Keywords

computer interfaces; concurrency control; formal verification; hardware-software codesign; interconnected systems; logic partitioning; software tools; synchronisation; PISH co-design system; concurrent processes interface generation; hardware/software co-synthesis; hardware/software codesign; independent interface generation; interconnections; layered interface structuring; multi-layer interface models; partitioning process formal verification techniques; process level communication implementation abstraction; software tools; synchronous communication; system target architecture; Application specific integrated circuits; Computer architecture; Digital systems; Hardware; Process design; Real time systems; Software prototyping; Software systems; Time to market; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on

Print_ISBN

0-7695-1807-9

Type

conf

DOI

10.1109/SBCCI.2002.1137645

Filename

1137645