• DocumentCode
    38677
  • Title

    Design and Implementation of a Low-Complexity Symbol Detector for Sparse Channels

  • Author

    Yanjie Peng ; Xinming Huang ; Klein, Andrew G. ; Kai Zhang

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., Worcester, MA, USA
  • Volume
    21
  • Issue
    8
  • fYear
    2013
  • fDate
    Aug. 2013
  • Firstpage
    1506
  • Lastpage
    1515
  • Abstract
    In this paper, we present a low-complexity symbol detector for communication channels which have long spanning durations but a sparse multipath structure. Traditional maximum-likelihood sequence estimation using the Viterbi algorithm can provide optimal error performance for eliminating the multipath effect, but the hardware complexity grows exponentially with channel length and it is not practical for long sparse channels. We implement a near-optimal algorithm and its architecture by cascading an adaptive partial response equalizer (PRE) with an iterative belief propagation (BP) detector. A sparse channel is first equalized by a PRE to a target impulse response (TIR) with only a few nonzero coefficients remaining. The residual intersymbol interference is then canceled by a BP detector whose complexity is solely dependent on the number of nonzero coefficients in the TIR. Moreover, we present a pipeline high-throughput implementation of the detector for channel length 30 with quadrature phase-shift keying modulation. The detector can achieve a maximum throughput of 206 Mb/s with an estimated core area of 3.162 mm2 using 90-nm technology node. At a target frequency of 515 MHz, the dynamic power is about 1.096 W.
  • Keywords
    equalisers; iterative methods; phase shift keying; telecommunication channels; TIR; Viterbi algorithm; adaptive partial response equalizer; bit rate 206 Mbit/s; communication channels; dynamic power; frequency 5.15 MHz; low-complexity symbol detector; maximum-likelihood sequence estimation; multipath effect; near-optimal algorithm; optimal error performance; power 1.096 W; quadrature phase-shift keying modulation; sparse channels; sparse multipath structure; target impulse response; Algorithm design and analysis; Complexity theory; Decoding; Detectors; Least squares approximation; Parity check codes; Throughput; Belief propagation (BP); low complexity; partial response equalizer; sparse channel; symbol detection;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2012.2211902
  • Filename
    6294462