Virtual in-circuit emulation for timing accurate system prototyping

This paper presents a novel HW/SW verification methodology called virtual in-circuit emulation, that is suitable for a platform-based design paradigm, where the main objective of co-verification is to validate the interaction between an existing core processor and some application-specific peripheral system. The proposed co-verification solution shares with conventional emulation schemes the possibility of performing both functional and timing-accurate validation with the same accuracy of the hardware, and greater speed than simulation software, yet it achieves this at a minuscule fraction of the cost of a conventional emulation system. We have validated the virtual in-circuit emulation paradigm on a real board hosting an ARM core and various hardware peripherals running an embedded application, that has been interfaced to a custom-designed I/O unit for the acquisition of data samples, described in SystemC.