DocumentCode
388089
Title
A family of ADPCM coders implemented on real-time hardware
Author
Cox, Richard V.
Author_Institution
AT&T Bell Laboratories, Murray Hill, New Jersey
Volume
12
fYear
1987
fDate
31868
Firstpage
964
Lastpage
967
Abstract
Recently, work in ADPCM speech coding has focused on using the adaptive predictors, already included in the coder algorithm, as the basis for noise shaping and post-filtering. This technique is based on improving the perceived quality of the signal -- no actual improvement in signal-to-noise ratio is possible. The original work was performed with an intended application of improving the performance of 16 and 24 kbps ADPCM. We have made extensions of this work for lower bit rates. Specifically we have looked at reducing the sampling rate by use of digital interpolation and at extending the technique to quantization rates as low as one bit per sample. The algorithms we have implemented run at rates in the range of 6 to 16 kbps. The coders below 9 kbps are probably not useful because their quality is too poor, but they do demonstrate the power of the noise shaping and post-filtering concept. The 9, 12 and 16 kbps coders would be useful in applications requiring a low complexity coder with only a single encoding. This paper describes the algorithms, their implementation using the WE (R) DSP32 signal processor, and their performance.
Keywords
Bit rate; Encoding; Hardware; Interpolation; Noise shaping; Quantization; Sampling methods; Signal processing algorithms; Signal to noise ratio; Speech coding;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '87.
Type
conf
DOI
10.1109/ICASSP.1987.1169808
Filename
1169808
Link To Document