VLSI bit-sequential architectures for digital signal processing

Increasing digital signal processing requirements coupled with developing VLSI circuit capabilities suggest that new architectures may be necessary for many signal processing applications. These new architectures must be compatible with the high density and planar layout features of VLSI circuits. Characteristics of parallel and serial multipliers for high-speed digital signal processing are discussed along with their respective implications for VLSI circuit realizations. Advantages of a bit-sequential approach to large-scale digital signal processors are presented, and the characteristics of a single-chip design for an image filter with 16, 12×12-bit multipliers followed by a tree adder structure are summarized.