Design and implementation of multi-channel high speed HDLC data processor

Author

Lu, Yuanlin ; Wang, Zhigong ; Qiao, Lufeng ; Huang, El

Author_Institution

Inst. of RF & OE ICs, Southeast Univ., Nanjing, China

Volume

2

fYear

2002

fDate

29 June-1 July 2002

Firstpage

1471

Abstract

This paper presents the design of a multi-channel high speed HDLC data processor that can processes 128 logic channel HDLC data simultaneously. Its logic function and communication protocol coherence has been verified successfully by a real-time operation system - Vx Works through FPGA. In the system, this multi-channel HDLC processor connects with 8 El physical links, and all 128 logic channel data separated from 256 timeslots of 8 El frames are processed by this single HDLC processor by using time multiplex technology. Compared with other communication chips of the similar type, this circuit structure takes more advantages in chip resources´ taking up and channel management.

Keywords

field programmable gate arrays; high-speed integrated circuits; microprocessor chips; protocols; time division multiplexing; FPGA; VxWorks; circuit design; communication protocol; logic function; multi-channel high-speed HDLC data processor; real-time operation; time multiplex technology; Communication system control; Computer errors; Cyclic redundancy check; Error correction; Field programmable gate arrays; Hardware; Logic; Polynomials; Process design; Protocols;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on

Print_ISBN

0-7803-7547-5

Type

conf

DOI

10.1109/ICCCAS.2002.1179057

Filename

1179057