Split-Drain Magnetic Field-Effect Transistor Channel Charge Trapping and Stress Induced Sensitivity Deterioration

This paper proposed an analytical model on the deterioration of magnetic sensitivity of sectorial split-drain magnetic field-effect transistors (SD-MAGFETs). The deterioration is governed by the trap fill rate at the channel boundary traps, which is geometric dependent. Experimental results are presented which show good consistency with the analytical derivation. The deterioration is the most severe at a sector angle of 54.6°, which shows a design tradeoff with sensing hysteresis. Design guidelines for sectorial SD-MAGFET to obtain high sensitivity hysteresis and slow sensitivity deterioration are also presented which provide important information for efficient design.