Simulated annealing based analog circuit synthesizer

This paper reports a synthesis system for analog circuits based on a simulated annealing (SA) algorithm. The effects of various SA parameters on the performance of the synthesis system are studied. The circuit synthesizer starts with an over-designed circuit library. Based on the specification from the user, the system developed explores through the design space of suitable circuit configurations, of which the SA process removes redundant components, if any. The final circuit generated is one that gives the closest performance to the specification. The input specifications to the system are defined in terms of the circuit performances that can be simulated.