Technique to design MLP networks in CMOS technology with adjustment of the backpropagation algorithm

The implementation of CMOS multipliers have been based on the use of either analog circuits for continuous time signal processing or switched current techniques for discrete time processing, once current mode topologies have become a trend for IC designers in low voltage applications. In this work we perform an analysis of some techniques for implementing the basic building blocks in a neural network using the IC technology for analog signal processing. Even though we focus on the operation of MOS devices in the strong inversion region deep into saturation, some aspects of the synapses in the weak inversion region are also explained, which has been accomplished through the use of classical asymptotical models for the drain current.