Baseband ASIP design for SDR

Author

Liu Dake

Author_Institution

Lab. of Applic. Specific Instruction-set Processors, Beijing Inst. of Technol., Beijing, China

Volume

12

Issue

7

fYear

2015

fDate

Jul-15

Firstpage

60

Lastpage

72

Abstract

Baseband ASIP designs for handsets are discussed based on the author´s R&D backgrounds. Algorithms for 4G, 3G, and WLAN are analyzed and selected for implementation based on the trade off of cost and performance with power consumption in mind. A SDR ASIP baseband system architecture is proposed for 4G and 3G mobile handsets. Function partitions for heterogeneous symbol processors are introduced to get higher performance over cost. Three structures for DFE, FFE, and Matrix symbol ASIP are proposed. The concept of bit parallel processor is introduced. Challenges of baseband processors for UDN of 5G were briefly introduced. Conclusions on ASIP architecture and system design are given for different baseband processors on different products.

Keywords

3G mobile communication; 4G mobile communication; 5G mobile communication; application specific integrated circuits; instruction sets; matrix algebra; parallel processing; power consumption; software radio; wireless LAN; 3G mobile handset; 4G; 5G; DFE; FFE; R&D; SDR; UDN; WLAN; application specific instruction-set processor; baseband ASIP design; baseband processor; bit parallel processor; digital front end; heterogeneous symbol processor; matrix symbol; power consumption; software defined radio; wireless local area network; Baseband; Forward error correction; OFDM; Payloads; Program processors; Radio transmitters; Receivers; SDR; architecture selection; baseband ASIP;

fLanguage

English

Journal_Title

Communications, China

Publisher

ieee

ISSN

1673-5447

Type

jour

DOI

10.1109/CC.2015.7188525

Filename

7188525