Serial test interface: a novel architecture for self-tests of ASICs

The manufacturing cost per transistor has decreased exponentially for the last decade. The test cost however, has been decreasing at a much slower rate and now occupies a major portion in total cost of an application specific integrated circuit (ASIC). Recent advances with VLSI technology now enable microprocessors and ASICs to be packaged into fine pitch, high count packages, posing numerous testing challenges. In this paper a generic test interface for testing IP-modules within an ASIC is presented. This eliminates the need for customizing testing modules. The proposed architecture is also shown to test multiple IP-modules within an ASIC. The paper further shows the possibility of testing selected IP-modules within an ASIC. Addition of a single design enables testing of all modules within the chip. The test interface is common to all digital ASICs and packages itself on the outside of the ASIC to form boundary scan architecture. This module is called serial test interface. Five new pins are added for user interface to enable testing. The serial test interface is designed to test all kinds of IP-modules simultaneously bypassing desired IP-modules in the test mode. The paper presents an alternative approach to IEEE 1149.1 in implementing boundary scan. The simplicity of the design presented in the paper makes this idea novel.