Synthesis of complex control structures from behavioral SystemC models

In this paper, we present the results of a set of experiments we conducted in order to evaluate the viability of behavioral synthesis, relying on the tools available at the moment in the EDA market. To accomplish this we modelled a complex PCI bus interface in SystemC using a behavioral style of description. Then we tried to synthesize it by means of the Synopsis CoCentric SystemC compiler tool. The problems arisen during synthesis, in particular those concerned with the cycle-accurate timing behavior of the synthesized circuit, were addressed. After analyzing them, possible solutions were proposed, where possible. Finally, a summary of the pros and cons of the behavioral synthesis in SystemC is presented.