A novel CMOS front-end circuit with low power, low noise and variable gain for 5-GHz WLAN applications

Author

Lin, Min ; Wang, Haiyong ; Li, Yongming ; Chen, Hongyi

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

Volume

2

fYear

2002

fDate

4-7 Aug. 2002

Abstract

Incorporating the low-IF architecture, a 5-GHz WLAN receiver front-end chip is implemented in a 0.18 μm in CMOS technology. The chip contains a single-in differential-out low noise amplifier with 1.5dB noise figure (NF), 25dB voltage gain and less than 13mW power consumption, a folded structure downconversion mixer with 9.9dB single side band noise figure (SSB NF), 13.7dB voltage gain and +2.7dBm IIP3, consuming 10mA current under a 2V supply voltage. The chip also has a 12dB gain adjustment through a VGA cell placed in parallel with LNA´s input.

Keywords

CMOS analogue integrated circuits; integrated circuit noise; low-power electronics; mixers (circuits); radio receivers; radiofrequency amplifiers; radiofrequency integrated circuits; wireless LAN; 0.18 micron; 1.5 dB; 10 mA; 13 mW; 13.7 dB; 2 V; 25 dB; 5 GHz; 9.9 dB; CMOS front-end circuit; WLAN receiver; folded structure downconversion mixer; low-IF architecture; low-power variable gain amplifier; single side band noise figure; single-in differential-out low-noise amplifier; CMOS technology; Circuit noise; Differential amplifiers; Energy consumption; Gain; Low-noise amplifiers; Noise figure; Noise measurement; Voltage; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on

Print_ISBN

0-7803-7523-8

Type

conf

DOI

10.1109/MWSCAS.2002.1186849

Filename

1186849