DocumentCode
391745
Title
Energy-aware multiplier design in multi-rail encoding logic
Author
Di, Jia ; Yuan, J.S. ; Hagedorn, M.
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA
Volume
2
fYear
2002
fDate
4-7 Aug. 2002
Abstract
Energy-awareness indicates the scalability of the system energy with changing conditions and quality requirements. A novel technique, Signal Bypassing and Zero Insertion, to design energy-aware multiplier in multi-rail encoding logic is developed. The results show that multi-rail energy-aware designs have advantages not only in energy saving, but also in delay reduction.
Keywords
logic design; low-power electronics; multiplying circuits; energy-aware multiplier design; multi-rail encoding logic; signal bypassing; system scalability; zero insertion; Boolean functions; Circuits; Delay; Design methodology; Encoding; Energy dissipation; Logic design; Scalability; Signal design; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN
0-7803-7523-8
Type
conf
DOI
10.1109/MWSCAS.2002.1186856
Filename
1186856
Link To Document