Signal integrity improvement in the TMDS link at UXGA

Author

Singh, A. ; Massoth, W. ; Fields, U. ; Youn, S.Y. ; Parten, M.

Author_Institution

Texas Tech. Univ., Lubbock, TX, USA

Volume

2

fYear

2002

fDate

4-7 Aug. 2002

Abstract

Transition Minimized Differential Signaling (TMDS) link connecting a Digital Visual Interface (DVI) compliant Transmitter and Receiver between a PC and a Display Device was characterized at 162MHz, that is the UXGA pixel clock frequency. The transmission line model of the link was simulated using Pspice and it was observed from the simulation data as well as the data collected from bench that a matching source termination at the transmitter end in addition to the far end termination at the receiver improved the signal integrity. The improvements were seen in the eye at the receiver with considerable reduction in data dependent jitter. Currently the DVI Revision 1.0 does not specify the requirement of a source termination.

Keywords

SPICE; clocks; telecommunication signalling; timing jitter; transmission line theory; 162 MHz; Digital Visual Interface; Pspice; TMDS link; Transition Minimized Differential Signaling; UXGA; UXGA pixel clock frequency; data dependent jitter; matching source termination; signal integrity; signal integrity improvement; source termination; transmission line model; Equations; Frequency; Impedance; Jitter; Page description languages; Passive circuits; Reflection; Signal processing; Transmitters; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on

Print_ISBN

0-7803-7523-8

Type

conf

DOI

10.1109/MWSCAS.2002.1186890

Filename

1186890