Power/bit optimization of Δ-Σ ADCs using multi-bit quantizers

A model for the design of power/bit efficient single loop Δ-Σ analog-to-digital converter (ADC) modulators is developed and validated. Further, we demonstrate and validate experimentally that for high dynamic range ADCs (14-20 bits), 2nd order systems with 3 to 4 bit quantizers are power per bit (power/bit) optimal. Due to the wide architectural selection in quantizers, the scaling between 1st and subsequent integrators, and the SNR objective of the ADC, there can be a modest freedom in the number of quantizer bits (B), the order (L), and the over-sampling-ratio (OSR) for low power ADC designs. In the final analysis, multi-bit quantizers are shown to always offer an advantage in improving power/bit performance in both single loop and MASH Δ-Σ modulators.