DocumentCode
391883
Title
Design and use based on long-term measurements of analog floating-gate array circuits
Author
Kucic, Matt ; Hasler, Paul ; Smith, Paul
Author_Institution
Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Volume
1
fYear
2002
fDate
4-7 Aug. 2002
Abstract
Presented are handling and use issues to consider when using floating-gates in analog circuits, such as where to set bias voltages to reduce long-term effects and conditions to avoid when powering up and down the system. Designs to compensate for long-term changes resulting from global disturbances are presented, both for computational blocks as well as bias currents using floating-gates. Lastly, long-term data from an array of floating-gates is presented demonstrating their ability to hold charge over time.
Keywords
CMOS analogue integrated circuits; analogue processing circuits; arrays; compensation; integrated circuit design; integrated circuit measurement; integrated circuit reliability; analog floating-gate array circuits; bias currents; bias voltages; global disturbances; long-term effects; long-term measurements; Analog circuits; Degradation; Digital systems; EPROM; MOS capacitors; Nonvolatile memory; Parasitic capacitance; Tunneling; Voltage; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN
0-7803-7523-8
Type
conf
DOI
10.1109/MWSCAS.2002.1187215
Filename
1187215
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