Capacitor coupling threshold logic

A novel high-speed dynamic CMOS capacitor coupling threshold logic (CCTL) family is proposed in this paper. In the proposed logic family, all the input signals are coupled to one transistor gate of a differential transistor pair through coupling capacitors. A reference signal is coupled to the other transistor gate of the transistor pair. The voltage difference between these two gates is sensed by a sense amplifier to generate two complementary logic outputs. For CCTL gates with a large number of inputs, the transistor count, interconnections and parasitic capacitances along the signal path are significantly reduced, which results in high switching speed and small chip area. Furthermore, there is no DC power dissipation in CCTL gates. Additionally, CCTL gates are able to provide two complementary logic outputs at the same time, making CCTL suitable for easy implementation of complex logic functions. CCTL can be fabricated with a standard double-polysilicon CMOS process. This paper presents design examples of typical CCTL gates, which have been simulated with 0.18 μm TSMC process models to demonstrate superior switching speed compared to static CMOS logic and dynamic Domino logic at the expense of slightly higher dynamic power dissipation.