Filling the via hole of IC by VPES (vacuum printing encapsulation systems) for stacked chip (3D packaging)

Author

Okuno, A.

Author_Institution

SANYU REC Co., Ltd., Osaka, Japan

fYear

2002

fDate

4-6 Dec. 2002

Firstpage

133

Lastpage

138

Abstract

The most important process for developing 3D packaging, especially wafer stacking, is studied in this paper. That is, the process of filling the via hole. Via holes need to be filled with conductive paste for connection or non-conductive paste for reliability. VPES is useful for the process of filling the paste in small via holes. And this process is also suitable for filling via holes of functional substrates and glass. Many kinds of paste (both conductive paste and nonconductive paste) were studied. It was important that the printing conditions (printing times, vacuum condition etc.) were different for each paste. Printing conditions for each paste were confirmed and the mechanisms for filling the via hole by VPES were identified. The printing conditions depend on the structure of the via hole (design, aspect ratio, diameter and depth etc.), and also the properties of the filling paste (viscosity and thixotropic index etc.).

Keywords

chip scale packaging; encapsulation; integrated circuit interconnections; integrated circuit reliability; thixotropy; viscosity; 3D packaging; IC via hole filling; VPES; aspect ratio; conductive paste connections; glass; nonconductive paste; paste viscosity; printing conditions; printing times; reliability; stacked chip packaging; substrate; thixotropic index; vacuum printing encapsulation systems; via hole structure; wafer stacking; Chip scale packaging; Curing; Electronics packaging; Encapsulation; Filling; Integrated circuit packaging; Printing; Smart cards; Vacuum systems; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Materials and Packaging, 2002. Proceedings of the 4th International Symposium on

Print_ISBN

0-7803-7682-X

Type

conf

DOI

10.1109/EMAP.2002.1188826

Filename

1188826