DocumentCode
393397
Title
DFT timing design methodology for at-speed BIST
Author
Sato, Yasuo ; Sato, Motoyulu ; Tsutsumida, Koki ; Kawashima, Masatoshi ; Hatayama, Kazumi ; Nomoto, Kazuyulu
Author_Institution
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
fYear
2003
fDate
21-24 Jan. 2003
Firstpage
763
Lastpage
768
Abstract
Logic BIST is well known as an effective method for low cost testing. However, it is difficult to realize at-speed testing, as it requires a deliberate timing design in regard to logic design and layout of the chip. This paper presents a timing design methodology for at-speed BIST, using a multiple-clock domain scheme. Some experimental test results of large industrial designs using our custom tool "Singen", are also shown.
Keywords
built-in self test; clocks; design for testability; integrated circuit design; integrated circuit testing; logic CAD; logic testing; software tools; timing; DFT timing design methodology; Singen custom tool; at-speed BIST; at-speed testing; chip layout; industrial designs; logic BIST; logic design; low cost testing; multiple-clock domain scheme; timing design; Built-in self-test; Circuit testing; Clocks; Costs; Design for testability; Design methodology; Logic design; Logic testing; Phase locked loops; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN
0-7803-7659-5
Type
conf
DOI
10.1109/ASPDAC.2003.1195122
Filename
1195122
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