Dynamic operand modification for reduced power multiplication

We present and analyze a methodology to reduce power dissipation in binary multiplication. Our methodology is based on the observation that any n by n bit multiplication of two operands A and B can be expressed by a variety of products like e.g. A/spl middot/B, B/spl middot/A, (-A)/spl middot/(-B), -((-A)/spl middot/B), and so on, all specifying the same value, each of which being associated with a different energy consumption of the underlying multiplier computation. Given a first operand A and a second operand B, all modified operands of the product choices from the above have in common that they can easily be generated from A and B by conditional switching and complementation and that they can serve as inputs for a conventional binary multiplier with almost unchanged internal structure. We propose selection among the modified operand choices targeting reduced power dissipation within the multiplier. For the proposed operand selection schemes, the potential power savings is analyzed depending on the operand bit width n.