DocumentCode :
393931
Title :
Energy efficient DSP systems - architecture and algorithms issues
Author :
Magotra, Neeraj ; Siravara, Bharath ; Larimer, Jim
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Volume :
1
fYear :
2002
fDate :
3-6 Nov. 2002
Firstpage :
62
Abstract :
This paper presents some insights into the architecture of one of Texas Instrument´s (TI) most energy efficient digital signal processors (DSP), the TMS320C55x. It discusses key low-power architecture issues including the rationale used in making trade-offs that did not adversely affect performance while minimizing chip level power requirements. The paper also discusses some algorithm development centric issues to illustrate how algorithm level researchers can also contribute to the bottom line when it comes to decreasing power consumption of a DSP system.
Keywords :
digital signal processing chips; low-power electronics; power consumption; TMS320C55x; Texas Instruments; address data flow unit; chip level power requirements; data computation unit; digital signal processors; energy efficient DSP systems; instruction buffer unit; low-power architecture; power down mechanisms; CMOS technology; Computer architecture; Constraint optimization; Design optimization; Digital signal processing; Digital signal processing chips; Energy efficiency; Instruments; Signal processing algorithms; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Systems and Computers, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
ISSN :
1058-6393
Print_ISBN :
0-7803-7576-9
Type :
conf
DOI :
10.1109/ACSSC.2002.1197150
Filename :
1197150
Link To Document :
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