Title :
A Pseudo-2-D-Analytical Model of Dual Material Gate All-Around Nanowire Tunneling FET
Author :
Vishnoi, Rajat ; Kumar, M.J.
Author_Institution :
Dept. of Electr. Eng., IIT Delhi, New Delhi, India
Abstract :
In this paper, we have worked out a pseudo-2-D-analytical model for surface potential and drain current of a long channel p-type dual material gate gate all-around nanowire tunneling field-effect transistor. The model incorporates the effect of drain voltage, gate metal work functions, thickness of oxide, and silicon nanowire radius. The model does not assume a fully depleted channel. With the help of this model, we have demonstrated the accumulation of charge at the interface of the two gates. The accuracy of the model is tested using the 3-D device simulator Silvaco Atlas.
Keywords :
field effect transistors; nanoelectronics; nanowires; semiconductor device models; tunnel transistors; work function; 3D device simulator Silvaco Atlas; charge accumulation; drain current; drain voltage effect; field-effect transistor; fully depleted channel; gate metal work functions; long channel p-type dual material gate all-around nanowire tunneling FET; oxide thickness; pseudo2D-analytical model; silicon nanowire radius; surface potential; Electric potential; Logic gates; Mathematical model; Numerical models; Silicon; Solid modeling; Tunneling; 2-D modeling; ON-state current; dual material gate (DMG); gate all-around (GAA); nanowires; subthreshold swing (SS); tunneling field-effect transistor (TFET); tunneling field-effect transistor (TFET).;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2014.2321977