Advanced self-organizing maps using binary weight vector and its digital hardware design

Author

Yamakawa, Takeshi ; Horio, Keüchi ; Hiratsuka, Tomokazu

Author_Institution

Graduate Sch. of Life Sci. & Syst. Eng., Kyushu Inst. of Technol., Fukuoka, Japan

Volume

3

fYear

2002

fDate

18-22 Nov. 2002

Firstpage

1330

Abstract

Many co-processors which are designed for learning of self-organizing maps (SOM) have been proposed in order to reduce the processing time. However, hardware in which all processes of the learning of the SOM are achieved is not realized, because it needs many complex calculations. In this study, a new learning algorithm of the SOM in which input vectors and weight vectors are represented as binary data is proposed. The effectiveness of the proposed algorithm is verified by designing the digital hardware of the proposed algorithm using HDL.

Keywords

digital circuits; neural chips; self-organising feature maps; unsupervised learning; vectors; Euclidean distance; SOM; binary weight vector; digital hardware design; learning algorithm; self-organizing maps; Algorithm design and analysis; Character recognition; Clocks; Coprocessors; Design engineering; Euclidean distance; Frequency; Hardware design languages; Self organizing feature maps; Systems engineering and theory;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Information Processing, 2002. ICONIP '02. Proceedings of the 9th International Conference on

Print_ISBN

981-04-7524-1

Type

conf

DOI

10.1109/ICONIP.2002.1202837

Filename

1202837