A novel design technique for very low voltage MOS translinear circuits

A novel technique for operating MOS translinear loops at very low supply voltages is presented. It is based on the use of a biasing cell recently reported and named "flipped voltage follower", that allows to create a very low impedance node in the translinear loops with a controllable and well-defined DC voltage even for large current swings, thus relaxing the supply voltage requirements for a given input current range. Measurement results of a 1.5V MOS translinear loop circuit implementing the square-root operator and fabricated in a 2.4μm CMOS process confirm the viability of the proposed approach.