A novel design technique for very low voltage MOS translinear circuits

Author

Lopez-Martin, Antonio J. ; Carlosena, Aljonso ; Ramirez-Angulo, Jaime

Author_Institution

Dept. of Electr. & Electron. Eng., Public Univ. of Navarra, Pamplona, Spain

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

A novel technique for operating MOS translinear loops at very low supply voltages is presented. It is based on the use of a biasing cell recently reported and named "flipped voltage follower", that allows to create a very low impedance node in the translinear loops with a controllable and well-defined DC voltage even for large current swings, thus relaxing the supply voltage requirements for a given input current range. Measurement results of a 1.5V MOS translinear loop circuit implementing the square-root operator and fabricated in a 2.4μm CMOS process confirm the viability of the proposed approach.

Keywords

CMOS analogue integrated circuits; analogue processing circuits; integrated circuit design; low-power electronics; operational amplifiers; 1.5 V; 2.4 micron; CMOS process; design technique; flipped voltage follower; low-voltage MOS translinear loop circuit; square-root operator; CMOS process; Circuits; Impedance; Low voltage; MOSFETs; Modems; Output feedback; Signal processing; Threshold voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205488

Filename

1205488