CMOS optical receiver chipset for gigabit Ethernet applications

This paper describes a 1.25-Gb/s simplified CMOS optical receiver chipset for gigabit Ethernet applications, consisting of a transimpedance amplifier (TIA) and a clock and data recovery (CDR) circuit. The TIA takes a fully differential regulated cascode configuration, demonstrating 700 MHz bandwidth for 1 pF photodiode capacitance, 80 dBΩ transimpedance gain, -17 dBm sensitivity for BER of 10^-12, and 27 mW power consumption. In our design, the postamplifier is omitted due to the large voltage swing of the TIA and to the high sensitivity of the proposed CDR. The CDR takes a half-rate clock technique and thus removes the necessity of a 1:2 demultiplexer. It achieves 40 mV_pp sensitivity due to the high sensitivity phase detector. The RMS clock jitter and data jitter are measured to be 3.9 ps_rms and 20.2 ps_rms, respectively. Two chips dissipate 127 mW from a single 2.5 V supply.