A low-voltage compatible two-stage amplifier with ≥120 dB gain in standard digital CMOS

This paper presents a low-voltage compatible 120 dB gain two-stage amplifier in standard digital CMOS with ≤3 transistors between V_DD and V_SS. The first stage uses positive feedback to increase the output impedance and DC gain. A MOS precision voltage attenuator, output level monitoring circuits (OLMC) and a digital tuning network are used to achieve conductance cancellation over large output swings and process and temperature variations. The first stage was fabricated and tested, achieving ≥76 dB DC gains over 2Vpp output swings. A modest-gain 2nd stage eliminates the need for OLMC and significantly improves linearity. The two stage amplifier can achieve ≥120 dB DC gains (by simulation, or 110 dB projected from test results) over 2Vpp output swings with PM ≥56° at UGF ≥ 120 MHz when VDD = 3.5V.