Performance optimization in micro-power, low-voltage log-domain filters in pure CMOS technology

Author

Maniero, Andrea ; Gerosa, Andrea ; Neviani, Andrea

Author_Institution

Dept. of Inf. Eng., Padova Univ., Italy

Volume

1

fYear

2003

fDate

25-28 May 2003

Abstract

The effect of parasitic capacitance on a basic building block of pure CMOS log-domain filters is discussed in this paper. The drawn analysis clearly highlights a basic trade-off between the system dynamic range and its bandwidth and helps to single out a design solution that optimizes the circuit performance. Such a procedure is exemplified with the design of a third order log-domain low-pass filter, operating in class AB. The circuit is fully integrated in a pure 0.8 μm CMOS technology, including signal compressor and expander, and operates down to 1.2 V. The dynamic range is larger than 51 dB and the whole circuit dissipates less than 70 μA.

Keywords

CMOS analogue integrated circuits; circuit optimisation; circuit simulation; compandors; integrated circuit design; integrating circuits; low-pass filters; low-power electronics; 0.8 micron; 1.2 V; 70 muA; CMOS filters; Seevink integrator; class AB operating circuit; dynamic range/bandwidth trade-off; filter performance optimization; low-voltage log-domain filters; micro-power filters; parasitic capacitance effects; signal compressor; signal expander; third order low-pass filter; Bandwidth; CMOS technology; Circuit optimization; Design optimization; Dynamic range; Integrated circuit technology; Low pass filters; Parasitic capacitance; Performance analysis; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205626

Filename

1205626