DocumentCode
396466
Title
Robust beamformer design by power minimization and its unconstrained partitioned implementation
Author
Yu, Zhu Liang ; Er, Meng Hwa
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
Volume
4
fYear
2003
fDate
25-28 May 2003
Abstract
A robust array beamformer design method by power minimization and its unconstrained partition implementation is proposed in this paper. An orthogonal blocking matrix is obtained through the proposed method. The new blocking matrix ensures that a desired look-direction response of the processor over a frequency band of interest can be closely approximated. Furthermore, if the spectrum of the target signal is known a priori, such as in microphone array application where the statistical property of speech is known, the new method may use fewer/less degree of freedom. This new method also provide a theoretical support for the derivation of the blocking matrix through array calibration. Simulation results show that the effectiveness of the proposed method.
Keywords
array signal processing; calibration; matrix algebra; minimisation; array beamformer; array calibration; look-direction response; orthogonal blocking matrix; power minimization; robust beamformer design; unconstrained partitioned implementation; wideband array processor; Array signal processing; Calibration; Delay; Design methodology; Frequency response; Interference constraints; Microphone arrays; Robustness; Sensor arrays; Wideband;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN
0-7803-7761-3
Type
conf
DOI
10.1109/ISCAS.2003.1205765
Filename
1205765
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