A reconfigurable channel codec coprocessor for software radio multimedia applications

This paper describes a coprocessor architecture for channel coding and decoding in software radio high bit rate applications. The proposed approach has been implemented in VHDL code. After a brief introduction about main target applications, and the motivation for the proposed architecture, we show the high level device layout, dwelling upon every single entity. Coprocessor functional behaviour has been analyzed by a Visual C++ simulator designed to this aim; in this document we show some of the most significant simulation results.